This invention relates to a circuit arrangement for forming a speed-proportional output voltage from a speed-proportional pulse sequence.
It is known to obtain a speed-proportional d-c voltage from a speed-proportional pulse sequence by causing the pulses of the speed-proportional pulse sequence to trigger a time delay stage having constant voltage amplitude and duration and by integrating the voltage-time areas so formed. Since the time constant of the timing member of the time delay stage must be selected according to the highest speed to be measured, the output voltage obtained in this manner will have more or less ripple. Where, however, the speed control system has a wide speed setting range, such an output voltage is not suitable as the actual voltage value. One is therefore compelled to use other actual value speed generators in which the ripple of the output voltage is practically zero, in cases where a speed control system having a wide speed setting range is needed. This property is exhibited, for instance, by d-c commutator motors which are customarily used as actual value speed generators in speed controlled drives with analog control and manipulated variable inputs. D-c commutator motors have the disadvantage, however, that the life and the measuring accuracy especially at high speeds, decline very strongly due to brush wear. This disadvantage may be avoided by using brushless d-c motors. These, however, require much circuitry for the commutator, and the output voltage likewise has much ripple.